We are looking for a Senior Verification Engineer join our Multimedia IP team in Taiwan. As a Senior Verification Engineer, you'll develop and verify the latest multimedia IP in our GPU and SOC chips. In this position, you'll make a real impact in a dynamic, technology-focused company, and contribute to our world-class technology and powerful legacy.

What you will be doing:

• Verification of our display subsystem IPs.

• Collaborate with Architect, Design, and SOC teams to determine verification scope, develop strategies, implement test planning, and verify designs at subsystem level, cluster level, and full chip level.

• Complete task lists, checklists, and deliverables.

• Drive verification infrastructure and quality improvement initiatives, working closely with leaders on integration, automation, and development environments.

What we need to see:

• Master’s Degree in EE, CS, CE, or equivalent experience.

• 5+ years of design verification experience.

• 2+ years of technical leadership experience.

• Proficiency in SV/UVM/C/C++.

• Proven experience with IP verification at block level, subsystem level, cluster level, and full chip level.

• Ability to study and understand complex architecture and micro-architecture specs within a short time frame.

• Outstanding test debug skills.

• Excellent English written and verbal communication skills.

• Ability to drive meetings with IP teams and partners in English.

Ways to stand out from the crowd:

• Familiarity with SoC concepts such as CPU, memory, interconnects, clock/reset, security, etc.

• Background in leading subsystem level, cluster level or full chip level verification.

• Experience in building verification infrastructure in C/C++.

• Proficient in scripting with Python, Perl, tcl, Make, shell.

• Experience working in a globally distributed team.

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