We are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

What you'll be doing:

• You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.

• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

• Work in a cross-functional environment interacting with multiple teams.

• Work on project execution as well as methodology improvements.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 2+ years’ experience in ASIC Design and Timing

• Great understanding of timing and physical design fundamentals

• Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills as well as physical design/circuit skills for timing closure.

• Excellent problem solving and debugging skills for timing issues, timing constraints and clocking.

• Expertise in STA tools and methodologies for timing closure with a good understanding of deep sub-micron process effects.

• Strong background and experience in timing constraints generation, analysis and debug including SDCs.

• Knowledge of timing corners/modes, process variations and signal integrity related issues and modeling.

• Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and tools

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies.

• Strong interpersonal and communication skills and ability to collaborate with cross-functional teams.

Ways to stand out from the crowd:

• Deep understanding of CPU, GPU, SOC architecture and designs as well as ability to plan and craft timing critical paths.

• Background and expertise in high-speed and low-power design closure.

• Ability to develop new methodologies/flows as well as workflows to aid timing convergence.

NVIDIA is a pioneer in bringing groundbreaking technology to new markets. We have some of the most forward-thinking and hardworking people in the world working with us. If you're creative and autonomous, we want to hear from you!

The base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.