Senior Digital Circuit Design Engineer
We are now hiring for a Senior Logic and Digital Circuit Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.
As a member of our Mixed-Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground breaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the analog schematics and write SystemVerilog models that collects the functionality of those circuits in the most precise way.
What you'll be doing:
You will be working with ASIC controller teams to define a unified interface
Help in streamlining workflows with proper scripts to increase efficiency and enables reusability
Be actively involve in silicon bringup, build scripts that can be used for debug, QA, characterization and ATE
What we need to see:
You should have a B.S. or MS degree in Electrical Engineering or equivalent experience
5+ years of experience working in high-speed I/O digital design, knowledge at protocol level (SATA, PCIE, USB) preferred
Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM
Proven experience with custom digital circuit design and adaptation algorithms, such as DFE, CTLE, CDR, and offset cancellation
Experience with static timing tools (nanotime, primetime) and formal verification tools
Have a strong background in Perl and Python scripting; If you have a background in computer architecture and deep learning, this is a plus