We are now looking for an ASIC Design Engineer – Hardware Methodology. As a member of our ASIC PD Methodology team, we expect you to have the attitude and aptitude to define, develop, and deploy various methodologies in the RTL-analysis and RTL-synthesis space. You'll be working on creating and maintaining product design methodologies, focusing on such tasks as RTL-synthesis and logic-equivalence checks, design optimization and automation of workflows.

What you'll be doing:

• Develop and enhance Synthesis/RTL-analysis workflows both at full-chip and block level.

• Partner with implementation teams, on both synthesis and P&R side, to understand their requirements and pain points if any, and enhance the methodology to cover for the same.

• Develop and deploy various methodologies based on technology updates, design requirements, and tool-feature/version updates and bug-fixes.

• Finetune the recipes for designs with aggressive PPA targets while ensuring logical equivalence is maintained.

• Develop custom scripts using tcl/perl/python to automate the post-processing of the reports/logs to present the results in a user-friendly format.

What we need to see:

• MS in Electronics/Electrical Engineering or Computer Science or equivalent experience

• 5+ years of relevant ASIC design experience ideally with a focus on RTL-synthesis

• Knowledge of Clock-domain crossing checks and RTL-Linting flows is a plus.

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