Custom SOC IP Verification Engineer
NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions! We are looking for special individuals with desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.
What you'll be doing:
Responsible for ASIC design verification for various processing blocks in a SOC. Work in key aspects of verification planning and execution, innovative verification methodology development, functional and code coverage closure
Participate in silicon architecture, micro-architecture reviews, collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution
Partner with internal and external teams, individual contributors and peers including customers
Drive development of silicon and platform verification strategy and methodology
Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing
Analyze, review supporting SOC and IP architecture and technical data, requirements and develop high quality verification plans, collaborate feedback to meet the needs of the program and customers
Support engineering teams to define, debug, implement and deliver total solutions around purpose-built ASICs
Define, implement and maintain key performance indicators for areas of responsibility
What We Need To See:
Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
Track record of first-pass success in ASIC Development
B.S. or M.S. degree in Computer Engineering or Electrical Engineering (or equivalent experience)
7+ years of experience
Experience working across multiple projects and adjusting priorities
Background with owning processing ASIC, IP or SoC design verification
Experience running and delivering complex mixed language UVM and C++ testbenches
Ability to deliver functional specs and creating comprehensive test plans
Ability to write directed and constraint random test to achieve coverage -driven verification closure
Experience developing tools and infrastructure using Perl or Python as well as strong background with AMBA protocols such as AXI,CHI, ATB, etc.
Hands-on experience with complex subsystems like ARM CPU complex, LPDDR, HBM, GPU’s, DLA, PCIE or Network on chip and with performance verification
Experience in GPU-based verification is desirable.