Senior Power Optimization and Analysis Engineer
We are now looking for a Senior Power Optimization and Analysis Engineer! NVIDIA prides ourselves in having energy efficient products. We believe that continuing to maintain our products' energy efficiency compared to competition is key to our continued success.
Our team is responsible for analyzing fullchip and unit-level power data, and driving ASIC teams to improve their units’ power efficiency; and is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Tegra SOCs. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
What You'll Be Doing:
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
Develop and share best practices for performing pre-silicon power analysis.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype a new architectural feature in Verilog and analyze power.
What We Need To See:
MS (or equivalent experience) with 5+ years of experience or PhD in related fields.
Strong understanding of concepts of energy consumption, estimation, data movement and low power design.
Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect).
Good verbal/written English and interpersonal skills; much collaboration with design teams is expected.
Strong coding/automation skills, preferably in Python, Perl, and C++.
Desire to bring data-driven decision-making and analytics to improve our products.